1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a thin film transistor substrate of horizontal electric field type liquid crystal display device and fabricating method thereof.
2. Description of the Related Art
Generally, liquid crystal displays (LCD) devices control light transmittance of liquid crystal using an electric field, to thereby display a picture. The liquid crystal displays are largely classified into a vertical electric field type and a horizontal electric field type depending upon the direction of the electric field driving the liquid crystal. The vertical electric field type drives a liquid crystal in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on the upper and lower substrate. The vertical electric field type has the advantage of a large aperture ratio while having the drawback of a narrow viewing angle of about 90°. The horizontal electric field type drives a liquid crystal in an in plane switch (IPS) mode with a horizontal electric field between the pixel electrode and the common electrode arranged in parallel to each other on the lower substrate. The horizontal electric field type has the advantage of a wide viewing angle of about 160°. Hereinafter, the liquid crystal display of horizontal electric field type will be described in detail.
The horizontal electric field type includes a thin film transistor array substrate (i.e., a lower substrate) and a color filter substrate (i.e., an upper substrate) that oppose each other and are joined to each other. A spacer is positioned between the two substrates to uniformly maintaining a cell gap between the two substrates. A liquid crystal material fills the cell gap between the two substrates. The thin film transistor array substrate includes a plurality of signal wirings for forming a horizontal electric field in each pixel, a plurality of thin film transistors and an alignment film for aligning the liquid crystal. The color filter substrate includes a color filter for implementing a color, a black matrix for preventing light leakage and an alignment film for aligning the liquid crystal.
In a horizontal electric field type liquid crystal display, the complicated fabrication of the thin film transistor substrate is a major cost factor in the manufacturing of the liquid crystal display panel because it involves a plurality of masking processes. For example, one mask process includes a lot of processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes. In order to address this issue, thin film transistor substrates have been developed that can be produced with the reduced number of masking processes. Recently, a four-mask process that excludes one mask process from the standard five-mask process has been developed.
FIG. 1 is a plan view showing a structure of a thin film transistor substrate of a horizontal electric field type liquid crystal display made using the related art four-mask process. FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the line I–I′ and the line II–II′ in FIG. 1. As shown in FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 45 in such a manner as to cross each other with a gate insulating film 46 therebetween. A thin film transistor 6 is adjacent to each crossing. A pixel electrode 14 and a common electrode 18 are provided at a pixel area, which is defined by the gate line 2 and the data line 4 for the purpose of forming a horizontal field. A common line 16 is connected to the common electrode 18. The thin film transistor substrate also includes a storage capacitor 20 provided at an overlap portion between the pixel electrode 14 and the common line 16. Further, a gate pad 24 is connected to the gate line 2, a data pad 30 is connected to the data line 4 and a common pad 36 is connected to the common line 16. The gate line 2 supplies a gate signal to the pixel area 5 and the data line 4 supplies a data signal to the pixel area 5. The common line 16 supplies a reference voltage for driving the liquid crystal and is provided on one side of the pixel area 5 in parallel with the gate line 2 on the other side of the pixel area 5.
The thin film transistor 6 allows the pixel signal of the data line 4 to be charged and maintained on the pixel electrode 14 in response to the gate signal of the gate line 2. The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 14. Further, the thin film transistor 6 includes an active layer 48 defining a channel between the source electrode 10 and the drain electrode 12. The active layer 48 overlaps a gate insulating film 46 on the gate electrode 8.
The active layer 48 also overlaps the data line 4, lower data pad electrode 32 and upper storage electrode 22. An ohmic contact layer 50 for making an ohmic contact with the data line 4 is provided on the active layer 48. In addition, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and the upper storage electrode 22 are also provided on the active layer 48.
The pixel electrode 14 is connected, via a first contact hole 13 through a protective film 52, to the drain electrode 12 of the thin film transistor 6 and is provided within the pixel area 5. The pixel electrode 14 includes a first horizontal part 14A connected to the drain electrode 12 and provided in parallel with adjacent gate lines 2, a second horizontal part 14B overlapping the common line 16, and a finger part 14C provided in parallel between the first and second horizontal parts 14A and 14B.
The common electrode 18 is connected to the common line 16 and is provided within the pixel area 5. Specifically, the common electrode 18 is provided in parallel with the finger part 14C of the pixel electrode 14 within the pixel area 5. Accordingly, a horizontal electric field can be formed between the pixel electrode 14 to which a pixel signal is supplied via the thin film transistor 6 and the common electrode 18 to which a reference voltage is supplied via the common line 16. As a result, a horizontal electric field can be formed between the finger part 14C of the pixel electrode 14 and the common electrode 18. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate by such a horizontal electric field are rotated due to the dielectric anisotropy. Transmittance of a light transmitting the pixel area 5 is differentiated depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 20 includes an upper storage electrode 22 overlapping the common line 16 with the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 therebetween. The storage capacitor 20 further includes a pixel electrode 14 connected, via a second contact hole 21 provided in the protective film 52, to the upper storage electrode 22. The storage capacitor 20 allows a pixel signal charged on the pixel electrode 14 to be stably maintained until the next pixel signal is charged.
The gate line 2 is connected, via the gate pad 24, to a gate driver (not shown). The gate pad 24 consists of a lower gate pad electrode 26 extending from the gate line 2 and an upper gate pad electrode 28 connected, via a third contact hole 27 through the gate insulating film 46 and the protective film 52, to the lower gate pad electrode 26. The data line 4 is connected via the data pad 30 to the data driver (not shown). The data pad 30 consists of a lower data pad electrode 32 extending from the data line 4 and an upper data pad electrode 34 connected, via a fourth contact hole 33 through the protective film 52, to the lower data pad electrode 32. The common line 16 receives a reference voltage from an external reference voltage source (not shown) through the common pad 36. The common pad 36 includes a lower common pad electrode 38 extending from the common line 16 and an upper common pad electrode 40 connected, via a fifth contact hole 39 through the gate insulating film 46 and the protective film 52, to the lower common pad electrode 38.
A method of fabricating the thin film transistor substrate having the above-mentioned structure using the four-round mask process will be described in detail with reference to FIGS. 3A to 3D. Referring to FIG. 3A, a gate metal pattern group including the gate line 2, the gate electrode 8 and the lower gate pad electrode 26, the common line 16, the common electrode 18 and the lower common pad electrode 38 is provided on the lower substrate 45 by a first mask process.
The gate metal pattern group is formed by first forming a gate metal layer on the upper substrate 45 by a deposition technique, such as sputtering. Then, the gate metal layer is patterned by photolithography and an etching process using a first mask, to thereby form the gate metal pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, common electrode 18 and the lower common pad electrode 38. The gate metal layer is formed from a metal, such as aluminum-alloy, chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3B, the gate insulating film 46 is coated onto the lower substrate 45 provided with the gate metal pattern group. Further, a semiconductor pattern including the active layer 48 and the ohmic contact layer 50, and a source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and the upper storage electrode 22 are provided on the gate insulating film 46 by a second mask process. More specifically, the gate insulating film 46, an amorphous silicon layer, an n+ amorphous silicon layer and a source/drain metal layer are sequentially provided over the lower substrate 45 having the gate metal pattern group by the appropriate deposition techniques, such as plasma enhanced chemical vapor deposition (PECVD) and/or sputtering. Herein, the gate insulating film 46 is formed from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is made from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy.
Then, a photo-resist pattern is formed on the source/drain metal layer by the photolithography using the second mask. In this case, a diffractive exposure mask having a diffractive exposing part corresponding to a channel portion of the thin film transistor is used as the second mask, thereby allowing a photo-resist pattern of the channel portion to have a height lower than other pattern portions.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern, to thereby define the source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the upper storage electrode 22.
Next, the photo-resist pattern having a relatively low height is removed from the channel portion by any ashing process and thereafter the source/drain metal pattern and the ohmic contact layer 50 of the channel portion are etched by a dry etching process. Thus, the active layer 48 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 52 includes first to fifth contact holes 13, 21, 27, 33 and 39 formed in the gate insulating film 46 by a third mask process. More specifically, the protective film 52 is deposited over the entire surface of the source/drain metal pattern group by a deposition technique, such as plasma enhanced chemical vapor deposition (PECVD). The protective film 52 is patterned by a photolithography and etching process using a third mask to define the first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 passes through the protective film 52 to expose the drain electrode 12. The second contact hole 21 passes through the protective film 52 to expose the upper storage electrode 22. The third contact hole 27 passes through the protective film 52 and the gate insulating film 46 to expose the lower gate pad electrode 26. The fourth contact hole 32 passes through the protective film 52 to expose the lower data pad electrode 32. The fifth contact hole 30 passes through the protective film 52 and the gate insulating film 48 to expose the lower common pad electrode 38. If the source/drain metal is formed from a metal having a high dry-etching ratio, such as molybdenum (Mo), then the first, second and fourth contact holes 13, 21 and 33 will respectively pass through the drain electrode 12, the upper storage electrode 22 and the lower data pad electrode 32 so as to expose side surfaces of these electrodes. The protective film 50 is formed from an inorganic material identical to the gate insulating film 46, or an organic material having a low dielectric constant, such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).
Referring to FIG. 3D, a transparent conductive film pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40 are provided on the protective film 52 by a fourth mask process. More specifically, a transparent conductive film is coated onto the protective film 52 by a deposition technique, such as sputtering. Then, the transparent conductive film is patterned by a photolithography and etching process using the fourth mask to form the transparent conductive pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40. The pixel electrode 14 is electrically connected, via the first contact hole 13, to the drain electrode 12 while also being electrically connected, via the second contact hole 21, to the upper storage electrode 22. The upper gate pad electrode 28 is electrically connected, via the third contact hole 37, to the lower gate pad electrode 26. The upper data pad electrode 34 is electrically connected, via the fourth contact hole 33, to the lower data pad electrode 32. The upper common pad electrode 40 is electrically connected, via the fifth contact hole 39, to the lower common pad electrode 38. The transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
The related art thin film transistor substrate of horizontal electric field type and the fabricating method thereof as mentioned above uses a four-round mask process, thereby reducing the number of fabricating processes and hence reducing manufacturing cost in comparison with those using the five-round mask process. However, since the four-round mask process still is a complicated fabricating process. Thus, a further cost reduction is limited. There is still a need to simplify the fabricating process and reduce the manufacturing cost.